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Defect Oriented Testing For Cmos Analog And Digital Circuits

Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 1475749260
Size: 47.88 MB
Format: PDF, Mobi
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Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal

Essentials Of Electronic Testing For Digital Memory And Mixed Signal Vlsi Circuits

Author: M. Bushnell
Publisher: Springer Science & Business Media
ISBN: 0306470403
Size: 71.18 MB
Format: PDF, ePub
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The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.

High Performance Memory Testing

Author: R. Dean Adams
Publisher: Springer Science & Business Media
ISBN: 0306479729
Size: 23.29 MB
Format: PDF, ePub, Docs
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Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

A Designer S Guide To Built In Self Test

Author: Charles E. Stroud
Publisher: Springer Science & Business Media
ISBN: 1402070500
Size: 11.96 MB
Format: PDF, Docs
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A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test (BIST). This idea was first proposed around 1980 and has grown to become one of the most important testing techniques at the current time, as well as for the future. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented since 1980, along with their advantages and limitations. The BIST approaches include the Built-In Logic Block Observer, pseudo-exhaustive BIST techniques, Circular BIST, scan-based BIST, BIST for regular structures, BIST for FPGAs and CPLDs, mixed-signal BIST, and the integration of BIST with concurrent fault detection techniques for on-line testing. Particular attention is paid to system-level use of BIST in order to maximize the benefits of BIST through reduced testing time and cost as well as high diagnostic resolution. The author spent 15 years as a designer at Bell Labs where he designed over 20 production VLSI devices and 3 production circuit boards. Sixteen of the VLSI devices contained BIST of various types for regular structures and general sequential logic, including the first BIST for Random Access Memories (RAMs), the first completely self-testing integrated circuit, and the first BIST for mixed-signal systems at Bell Labs. He has spent the past 10 years in academia where his research and development continues to focus on BIST, including the first BIST for FPGAs and CPLDs along with continued work in the area of BIST for general sequential logic and mixed-signal systems. He holds 10 US patents (with 5 more pending) for various types of BIST approaches. Therefore, the author brings a unique blend of knowledge and experience to this practical guide for designers, test engineers, product engineers, system diagnosticians, and managers.

Defect Oriented Testing For Nano Metric Cmos Vlsi Circuits

Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 0387465472
Size: 14.18 MB
Format: PDF
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The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

Advances In Electronic Testing

Author: Dimitris Gizopoulos
Publisher: Springer Science & Business Media
ISBN: 0387294090
Size: 77.28 MB
Format: PDF, ePub
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This is a new type of edited volume in the Frontiers in Electronic Testing book series devoted to recent advances in electronic circuits testing. The book is a comprehensive elaboration on important topics which capture major research and development efforts today. "Hot" topics of current interest to test technology community have been selected, and the authors are key contributors in the corresponding topics.

Books In Print

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Size: 52.13 MB
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Books in print is the major source of information on books currently published and in print in the United States. The database provides the record of forthcoming books, books in-print, and books out-of-print.

Zuverl Ssigkeit Mechatronischer Systeme

Author: Bernd Bertsche
Publisher: Springer-Verlag
ISBN: 3540850910
Size: 15.54 MB
Format: PDF, Docs
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Das Buch behandelt die Zuverlässigkeitsbewertung mechatronischer Systeme – speziell in frühen Entwicklungsphasen. Herausforderung hierbei ist vor allem die ganzheitliche Betrachtung der Domänen Mechanik, Elektronik und Software sowie der unsicheren bzw. unvollständigen Daten. Neben der domänenübergreifenden Betrachtungsweise vertiefen die Autoren einzelne Themenaspekte, die der Zuverlässigkeitsbewertung in frühen Entwicklungsphasen dienen.